Kerala University 8th Semester B.Tech Previous Question Papers- Computer Architecture and Parallel Processing (CAP)

     Kerala University B.tech 8th Semester Computer Architecture and Parallel processing Previous University Question Papers

Module-I(4 Marks)

1. Distinguish between data parallelism and temporal parallelism?
2. Why the architecture of a vector processor improves the performance of programs that operate on vectors and matrices?
3. Explain how parallelism can be incorporated in uniprocessor system?
4. What are the advantages of vector processing?
5. What are the architectural methods used to increase the speed of computers?
6. For a pipeline with n stages, what is the ideal throughput? What prevents us from achieving this ideal throughput?
7. What are the properties of vector processors?
8. Define parallel processing?
9. What do you mean by the ‘speed up ‘of a pipeline processor?
10. What is a vectorising compiler?
11. For the efficiency of a pipelined floating point adder with 4 stages in processing 1000 instructions?
12. Give a comparison between pipelined computers and non pipelined computers using space- time diagrams?
13. Discuss Flynn’s classification of computer organization?
14. What is an arithmetic pipeline and how it is different from instruction pipeline?
15. Explain the interleaved memory organization?
16. Illustrate the spaces of data, information, knowledge and intelligence from the viewpoint of computer processing?
17. What is the difference between spatial parallelism and temporal parallelism?
18. Define the terms-Efficiency and Throughput of a linear pipeline?
19. How the performance of vector processors can be enhanced?
20. Explain relevance of parallel processing for high speed computing?
21. What is meant by vector processing?
22. Do you think that multiplicity of functional units increases the performance of a digital computer system? Why?

                                                Module I: Essay (20 marks)
1. Define the terms ‘structural hazard’, ‘control hazard’, and ‘data hazard’ in the context of pipelines .which of these hazards is addressed by a hardware branch prediction?
2. For other hazards suggest a way, either software or hardware, the effect of that hazard could be reduced?
3. With block diagram explain the properties of cyber-205 vector processor?
4. Consider a four stage floating point adder with 10ns delay per stage which equals the pipeline clock period?
i) What are the functions to be performed by four stages?
ii) Find the minimum number of periods required to add 100 floating point numbers f1+f2+…f100 using this pipeline adder.[Assume that the output Z of last stage can be routed back to either of two inputs X or Y of the pipeline].delays  equal to multiple of the clock period?.



5.Outline the principle of pipelined computer. Explain what is meant by pipeline hazards and describe the               different kinds of hazards which may be encountered? How these can be avoided?
6.Explain the parallel processing mechanisms in a uniprocessor computer with required block diagrams?
7.Explain the architecture of cray-1 with block diagram?
8.Explain how parallelism is achieved in uniprocessor systems?
9.What is the significance of feng’s classification computers?
10.Discuss the architectural differences between cray-1 and cyber-205?
11.Briefly explain the performance of pipelined digital computers?
12.Explain the principles of designing pipeline processors with examples and required figures?
13.Explain the architectural configurations of parallel computers with relevant block diagrams?
14.Explain the architecture of cyber-205 vector processor with block diagram?

Module II- (4 marks)

1. Compare static connection networks and dynamic interconnection networks?
2. What are the applications of iliac- 4?
3. Write an n log n algorithm for SIMD matrix multiplication?
4. Explain how3 the shuffle exchange network functions can be implemented with multistage omega networks?
5. Distinguish between synchronous and asynchronous parallel algorithms for multiprocessors?
6. What is meant by recirculating network?
7. What is meant by content-addressable memory and what are its advantages?
8. What is a cube interconnection network?
9. Explain the masking and data routing mechanisms in an array processor, briefly?
10. Write short notes on associate memory organization?
11. Differentiate between single stage and multistage networks?
12. What are the factors that determine the appropriate architecture of an interconnection network for an SIMD machine?
13. Discuss about shuffle –exchange and omega networks?
14. What are the differences between array processors and associative processors?
15. How will you classify array processing techniques?
16. Compare the features of array processing with vector processing?
17. Draw the basic block diagram to array processing computers?
18. What are dynamic SIMD interconnection networks?
19. What are the factors that affect the performance of an interconnection network?
20. How to analyze the performance of array processors?

Module -II:Essay (20 Marks)

1. Consider an illiacmesh (8*8) ,a binary hypercube and a barrel shifter, all with 64 nodes labeled n0,n1…n63.all network links are bidirectional.

a) List all the nodes reachable from node n0 in exactly three steps for each of the three networks?
b)Indicate in each case the tight upper bound on the minimum number of routing steps needed to send data from any node ni to nj another node .
c) Repeat part (b) for a large network with 1024 nodes.

2. Explain briefly the architecture (with block diagram) hardware and software features and application requirements of iliac 4?
3. Explain the barrel - shifting function associated with SIMD computers
3.1. How many steps are required to broadcast an information item from one PE to all other PEs in each of the following single stage interconnection networks?
a) A shuffle exchange network.
b)A cube networks.

4.1. Explain the architecture of iliac-4 with block diagram?
4.2. Explain the following memory organizations for vector accesses?
               a)  S-access memory organization
               b)  C-access memory organization
               c)  C/S access memory organization

5. Explain the two architectural configurations of SIMD array processors with figures?
6. Explain the architecture of iliac-4 with relevant block diagram?
7. Draw and explain the system architecture of iliac-4?
8. Explain various techniques for improving the performance of vector processors?
9. How does masking and data routing mechanisms are performed in a SIMD array processors?
10. Explain briefly any four interconnection networks suggested for SIMD computers?
11. Explain the architecture of a massively parallel processor with relevant block diagram?
12. Explain static networks and dynamic networks in SIMD interconnection networks?
13. Describe the various parallel algorithms for array processors?

Module III (4 Marks)

1. In a data flow machine, what determines whether an instruction can be executed or not? Explain with example?
2. Describe deadlock detection and recovery associated with multiprocessor operating systems?
3. What are the advantages and disadvantages of loosely coupled architecture?
4. Describe the deadlock prevention and avoidance associated with multiprocessor operating systems?
5. Compare static data flow computer and dynamic data flow computer organization?
6. What are the various systolic array configurations?
7. Explain cache coherence problem?
8. What is bit slice and word slice processing?
9. What are the specific characteristics of systolic array architecture?
10. Illustrate and discuss the communication between processes in a multiprocessor environment?
11. What is meant by dataflow graph?
12. What is a systolic array?
13. Differentiate between tightly coupled and loosely coupled multiprocessor systems?
14. How data flow computers are different from traditional control flow computers?
15. Distinguish between static and dynamic dataflow computers?
16. How input output asymmetry is handled in a multiprocessor system?
17. What are the processor characteristics required for effective processing in a multiprocessor environment?

Module 3(Essay: 20 Marks)

1. Suppose you are designing a multiprocessor with a homogeneous collection of processing units with local memory.
1) What structure you would use to connect the processors together?
2) What network topologies would you consider? And why?
3) How would you determine the best design for this network?
                           2.1. What are the various systolic array configurations?
                            2.2. What is the difference between loosely coupled and tightly coupled parallel computers? Give one example of each of these parallel computer structures?
3.1. What are the two communication models for multiprocessors?
3.2. Draw data flow graphs to represent the following computations.
                       For iß1 to m do
                       Begin
                           C[i]ß0:
                       For jß1 to n do
                       C[i]ßc[i]+a(i,h)+b(j).    
4. Explain how the shuffle exchange network function can be implemented with multiple omega networks?
5. Describe any two bus arbitration algorithms?
6. Explain the architecture of C.mmp multiprocessor system with block diagrams?
7. Explain the architecture of static data flow computers?
8. Explain interprocessor communication mechanisms and deadlock. How to protect system from deadlocks?
9. Discuss the significance of parallel algorithms for parallel processing systems?
10. Explain tightly coupled multiprocessor configuration with private cache and without private cache?
11. Explain tightly coupled multiprocessor configuration with private cache and without private cache?
12. Describe briefly about operating systems configuration for a multiprocessor computer?